1. Field of the Invention
This invention concerns a dynamic random access memory (hereafter called DRAM) device. More particularly, this invention concerns a DRAM device which includes switching transistors between bit lines and a sensing amplifier.
2. Description of Related Art
The current discharged to the bit lines of a DRAM device during a read operation is increased in proportion to the increase in the capacitance of the bit lines. The increased capacitance causes a reduction in the sensing speed of a sensing amplifier which senses the voltage difference between the bit lines.
To increase the sensing speed, a DRAM device which includes switching transistors has been proposed. (see: National Convention Record, 1986 The Institute of Electronics and Communication Engineering of Japan, Part 2, P247)
FIG. 1 is a circuit diagram of a conventional DRAM device which includes a switching circuit 2. The switching circuit 2 includes two switching transistors CT1 and CT2 which are connected between a precharge/equalize circuit 1 and an active restore circuit 3. The precharge/equalize circuit 1 equalizes the potentials of the bit lines BL1 and BL2 and precharges them to half the voltage (1/2 Vcc) of the power source voltage Vcc. The precharge/equalize circuit 1 is activated and controlled by a precharge/equalize signal EQL.
Numeral 4 designates a sensing amplifier which includes two N-type MOS transistors N1 and N2. The respective gate electrodes of the MOS transistors N1 and N2 are connected to a respective sensing node SN1 and SN2, respectively.
The two sensing nodes SN1 and SN2 are connected to data lines DQ1 and DQ2 through column select transistors ST1 and ST1. The sensing amplifier 4 is activated and controlled by a latch signal L which is supplied to the gate of an N-type MOS transistor N3.
The data lines DQ1 and DQ2 are connected to the output terminals of inverters IV1 and IV2 which constitute a part of a data writing circuit DW. The two inverters IV1 and IV2 are supplied with output signals from the OR gates G1 and G2. The OR gates G1 and G2 are supplied with a complementary data signals DATA and DATA and an internal write enable signal WEi.
Referring to FIG. 2, a read and restore operation for the circuit illustrated in FIG. 1 will be explained. Assume that the memory cell MC1 connected to the bit line BL1 stores a Low level data (zero volt), and the bit lines BL1 and BL2 are precharged to half the voltage (1/2 Vcc) of the power source voltage Vcc.
When the word line WL1 is selected and the charge transfer transistor TM becomes conductive, the Low level data is read from the memory capacitor Cs. Thus, the potential of the bit line BL1 is lowered slightly from the 1/2 Vcc.
On the other hand, the dummy word line DWL2 is simultaneously selected when the word line WL1 is selected, and the charge transfer transistor TD in the dummy cell DC2 becomes conductive. Since the dummy cell capacitor Cd stores the 1/2 Vcc level, the potential of the bit line BL2 does not change from the 1/2 Vcc voltage.
In this condition, the potential of the bit enable signal BC becomes the ground potential Vss and the switching transistors CT1 and CT2 become non-conductive. Thus, the bit lines BL1 and BL2 are separated from the sensing amplifier 4 and the active restore circuit 3.
In this condition, by activating the sensing amplifier 4 by supplying a Vcc level latch signal L to the gate of the MOS transistor N3, the slight difference voltage between the bit lines BL1 and BL2 is sensed by the sensing amplifier 4 and the potential of the sensing node SN1 is lowered to the Vss level.
When the active restore circuit 3 is activated by being supplied with a Vcc level active restore signal AR, the potential of the sensing node SN2 is pulled-up to the Vcc level.
Then, the column select transistors ST1 and ST2 become conductive in response to a column decode signal CSLi, the potentials of the sensing nodes SN1 and SN2 are transferred to the data lines DQ1 and DQ2, and are amplified by the data buffer 5. The output of the data buffer 5 is then output to the data bus DL1 and DL2.
Then, the potential of the BC signal returns to the high level and the switching transistors CT1 and CT2 become conductive. Thus, the bit lines and the sensing nodes are connected, and the pontential of the bit line BL1 is lowered to the Vss level and the potential of the bit line BL2 is pulled-up to the Vcc level. In this way, the restore operation to the memory cell MC1 and the dummy cell DC2 is performed.
Thereafter, the selection of the word line WL1 and the dummy word line DWL2 is released. Then, the precharge/equalize circuit 1 is activated in response to the precharge/equalize signal EQL, and the bit lines BL1 and BL2 are precharged to 1/2 Vcc level.
In this way, the sensing speed is increased, since the large capacitances of the bit lines BL1 and BL2 are separated from the sensing amplifier 4 during the sensing operation except during the initial sensing period.
FIG. 3 is another conventional DRAM device which includes switching transistors. In this DRAM device, the switching transistors CT1 and CT2 are connected between the active restore circuit 3 and the sensing amplifier 4. Namely, the active restore circuit 3 is directly connected to the bit lines BL1 and BL2. Thus, the bit lines BL1 and BL2 are directly pulled-up to the Vcc potential by the active restore circuit 3. Therefore, the voltage drop due to the switching transistors CT1 and CT2 is solved, and the bit line potential is pulled-up to the Vcc level.
FIG. 4 is a timing chart showing a read and restore operation of the DRAM device of FIG. 3. As shown in FIG. 4, the switching transistors CT1 and CT2 are rendered non-conductive during the read period by being supplied with the low level BC signal. Thus, the sensing speed is increased, since the large capacitance due to the bit lines is separated from the sensing amplifier 4 during the sense operation except during the initial read period.
Referring now to FIGS. 5 to 8, a write operation will be explained. A row address signal (not shown) and a column address signal (not shown) are successively input from an external circuit, e.g., a CPU (Central Processor Unit), and a row address stored signal RAS is activated after the row address signal is input. Then, the row address signal is decoded by a row address decoder (not shown), and is applied to the word line WL1, for example. The column address signal is decoded by a column address decoder (not shown), and is applied to the column select transistors ST1 and ST2 as a column decode signal CSLi, for example.
The inventors of the present invention attempted to modify a bit enable signal generator 100 and an internal write enable signal generator 200 shown in FIGS. 5 and 6 to more effectively produce the bit enable signal BC and the internal write enable signal WEi, respectively.
Namely, the bit enable signal generator 100 shown in FIG. 5 includes a delay circuit 10 which receives the RAS signal. The output signal of the delay circuit 10 is applied to a NAND gate 14 through an inverter 11. The output of the inverter 11 is also applied to the NAND gate 14 through a delay circuit 12 and inverter 13.
The bit enable signal generator 100 generates a bit enable signal BC in response to the RAS signal. The low level period of the bit enable signal BC is determined by the delay time of the delay circuit 12.
The internal write enable signal generator 200 shown in FIG. 6 includes a delay circuit 20 which receives the RAS signal. The output signal of the delay circuit 20 is applied to a NOR gate 21. The NOR gate 21 is also supplied with the CAS signal and an external write enable signal WE. The output signal of the NOR gate 21 is applied to a NAND gate 26 through two inverters 22 and 23. The output signal of the inverter 23 is also applied to the NAND gate 26 through a delay circuit 24 and an inverter 25.
If the external write enable signal WE is activated after the activation of the CAS signal, the falling of the internal write enable signal WEi is determined by the falling of the external write enable signal WE, and the rising thereof is determined according to the delay time t3 of the delay circuit 24. Thus, by adjusting the delay time of the delay circuit 24 based on the timing of the BC signal, it is possible to insure the rising of the internal write enable signal WE after the rising of the bit enable signal BC.
However, when the external write enable signal WE is activated earlier than the CAS signal, namely at an early write mode, the rising of the internal write enable signal WEi is determined or responsive to the rising of the external write enable signal WE. Thus, the internal write enable signal WEi occasionally rises earlier than the rising of the bit enable signal BC.
In this condition, the switching transistors CT1 and CT2 are non-conductive. Thus, the input data can be transferred to the sensing amplifier 4, but not to the bit lines BL1 and BL2. Therefore, if the input data DATA and DATA are opposite with respect to the data of the bit lines, the data of the sensing amplifier 4 may be destroyed by the potential of the bit line when the switching transistor becomes conductive. Namely, as shown in FIG. 8, the voltages of the sensing nodes SN1 and SN2 are pulled to the voltages of the bit lines BL1 and BL2.
The same problem exists in the circuit of FIG. 1.